FSDLY=0, HSDLY=0, FSPHS=0, HSPHS=0, HSENA=0
Sampling Register
| HSENA | Half Speed serial flash clock Enable 0 (0): Disable divide by 2 of serial flash clock for half speed commands 1 (1): Enable divide by 2 of serial flash clock for half speed commands |
| HSPHS | Half Speed Phase selection for SDR instructions. 0 (0): Select sampling at non-inverted clock 1 (1): Select sampling at inverted clock |
| HSDLY | Half Speed Delay selection for SDR instructions. 0 (0): One clock cycle delay 1 (1): Two clock cycle delay |
| FSPHS | Full Speed Phase selection for SDR instructions. 0 (0): Select sampling at non-inverted clock 1 (1): Select sampling at inverted clock. This bit is also used in DQS mode and ignored when using non-DQS DDR instructions. |
| FSDLY | Full Speed Delay selection for SDR instructions. Select the delay with respect to the reference edge for the sample point valid for full speed commands. 0 (0): One clock cycle delay 1 (1): Two clock cycles delay. This bit is also used in DQS mode and ignored when using non-DQS DDR instructions. |
| DDRSMP | DDR Sampling point |